====== FPGA ======

<box 48% left | **FPGA Familien**>
  * [[.:cyclone_iv:start | Altera Cyclone IV]]
  * [[.:Spartan 2:start | Xilinx Spartan 2]]
  * [[.:Spartan 3:start | Xilinx Spartan 3]]
  * [[.:Virtex 2 Pro:start | Xilinx Virtex 2 Pro]]
</box>

<box 48% left | ** FPGA Boards am NTB:**>
  * [[.:Boards:DE0_Nano:start | Altera DE0-Nano]]
  * [[.:Cyclone IV:Altera DE2_115 | Altera DE2-115]]
  * [[.:spartan_3:xilinx_xc3s200_starter_board | Xilinx Spartan-3]]
  * [[.:Virtex 2 Pro:XUPV2P | Digilent Xilinx XUPV2P]]
</box>

<box 48% left | ** FPGA Tools:**>
  * [[Software:quartus_ii_web_edition:start | Altera Quartus II]]
  * [[Software:ise_webpack:start | Xilinx ISE]]
  * [[Software:Modelsim:start | ModelSim]]
  * [[.:Qsys:start | Qsys]]
</box>

<box 48% left | **Beispiele**>
   * [[.:BeispielPCIeGPIO:start | PCIe mit GPIO Interface]]
   * [[.:VHDLLibrary:start | NTB VHDL Library]]
</box>


<box 48% left | **VHDL Module Allgemein**>
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<box 48% left | **VHDL Module für Altera DE2-115**>
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