Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende ÜberarbeitungNächste ÜberarbeitungBeide Seiten der Revision | ||
embedded_systems:imx6:cb [2020-06-02 09:01] – graf | embedded_systems:imx6:cb [2022-09-21 09:19] – Urs Graf | ||
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* 1 x Konsole, 1 x UART | * 1 x Konsole, 1 x UART | ||
* 24 DIO | * 24 DIO | ||
- | * 8 Analog Out | + | * 8 Analog Out (+/-10V) |
</ | </ | ||
The board has a EP4CE22F17C8 FPGA from Altera which is connected over the EIM bus to the Colibri module. | The board has a EP4CE22F17C8 FPGA from Altera which is connected over the EIM bus to the Colibri module. | ||
- | * {{: | + | * {{: |
- | * github repository with Altium files, FPGA designs, and test application https://github.com/ntb-ch/cb20 | + | * github repository with Altium files, FPGA designs, and test application https://gitlab.ost.ch/ |
* [[#Known Errors]] | * [[#Known Errors]] | ||
- | * [[software: | + | * [[software: |
* Hardware configuration file for EEROS [[https:// | * Hardware configuration file for EEROS [[https:// | ||
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===== flink Configurations ===== | ===== flink Configurations ===== | ||
==== Standard FPGA Design ==== | ==== Standard FPGA Design ==== | ||
+ | The FPGA is driven by a 50MHz clock. The system incorporates a Avalon ALTPLL component which multiplies this clock with 4 leading to a internal clock of 200MHz. The flink blocks which depend on this clock must set their base clock setting accordingly. | ||
This configuration defines the following subdevices: | This configuration defines the following subdevices: | ||
^ flink component ^ unique id ^ id ^ nof channels ^ description ^ | ^ flink component ^ unique id ^ id ^ nof channels ^ description ^ | ||
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=== Test Program === | === Test Program === | ||
- | Unter https:// | + | There is a test program using [[http:// |
- | Das Testprogramm liest eine passende Hardware-Konfiguration ein. | + | There is a second application // |
- | * HwConfigCb20.json: alle Pins werden konfiguriert. Auf den analogen Ausgängen, den digitalen Ausgängen und den PWM-Ausgängen werden Werte ausgegeben. Die Encoder-Eingänge werden geloggt. | + | |
- | * HwConfigDb11.json: nur je vier Encoder-Eingänge, analoge Ausgänge, ready-Signale und das Enable-Signal werden konfiguriert. Zu dieser Hardware-Konfiguration gibt es ein spezielles Testprogramm | + | ==== FPGA Design with Watchdog and PPWA ==== |
+ | ^ flink component ^ unique id ^ id ^ nof channels ^ description ^ | ||
+ | | PWM | 0x1270C001 | 0 | 4 | | | ||
+ | | PPWA| 0x12706001 | 1 | 2 | | | ||
+ | | Watchdog| 0x12710001 | 2 | 1 | | | ||
+ | | FQD | 0x12706001 | 3 | 8 | | | ||
+ | | Analog Out | 0x12702001 | 4 | 8 | | | ||
+ | | Info Device | 0x12700001 | 5 | | cb20 with wdt, 28.5.2020| | ||
+ | | Dig I/O | 0x12705002 | 6 | 8 | | | ||
+ | | Dig I/O (Enable/ | ||
+ | The pins are assigned as with the standard configuration with the following exceptions: P11 has 4 PWM channels (pin 1 to 4), PPWA is on pin 5 and 6, Watchdog is on pin 7 (granted) and 8 (pwm). | ||
==== FPGA Design with MPU9250 ==== | ==== FPGA Design with MPU9250 ==== | ||
- | This design incorporates a SPI Connection | + | This design incorporates a SPI connection |
^ flink component ^ unique id ^ id ^ nof channels ^ description ^ | ^ flink component ^ unique id ^ id ^ nof channels ^ description ^ | ||
| PWM | 0x1270C001 | 0 | 4 | | | | PWM | 0x1270C001 | 0 | 4 | | | ||
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| Dig I/O (Enable/ | | Dig I/O (Enable/ | ||
- | [{{: | + | [{{: |
==== Known Errors ==== | ==== Known Errors ==== | ||
- | Falls CAN zur Ansteuerung eines Drives mit hoher Leistung verwendet wird, muss CAN GND zusätzlich angeschlossen werden. Dies ist auf dem Controller Board Versionen | + | If CAN is used to connect to a drive with high power, CAN GND must be connected. This connection is missing on the board version |
- | [{{: | + | [{{: |
- | [{{: | + | [{{: |