Infoportal
Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
| Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
| embedded_systems:imx6:cb [2020-06-03 16:44] – graf | embedded_systems:imx6:cb [2023-06-28 13:32] (aktuell) – Urs Graf | ||
|---|---|---|---|
| Zeile 25: | Zeile 25: | ||
| * 1 x Konsole, 1 x UART | * 1 x Konsole, 1 x UART | ||
| * 24 DIO | * 24 DIO | ||
| - | * 8 Analog Out | + | * 8 Analog Out (+/-10V) |
| </ | </ | ||
| The board has a EP4CE22F17C8 FPGA from Altera which is connected over the EIM bus to the Colibri module. | The board has a EP4CE22F17C8 FPGA from Altera which is connected over the EIM bus to the Colibri module. | ||
| - | * {{: | + | * {{: |
| - | * github repository with Altium files, FPGA designs, and test application https://github.com/ntb-ch/cb20 | + | * github repository with Altium files, FPGA designs, and test application https://gitlab.ost.ch/ |
| * [[#Known Errors]] | * [[#Known Errors]] | ||
| - | * [[software: | + | * [[software: |
| - | * Hardware configuration file for EEROS [[https://github.com/ntb-ch/ | + | * Hardware configuration file for EEROS [[https://gitlab.ost.ch/ |
| The FPGA configuration for the cb20 is made with [[https:// | The FPGA configuration for the cb20 is made with [[https:// | ||
| Zeile 64: | Zeile 64: | ||
| === Test Program === | === Test Program === | ||
| - | Unter https://github.com/ntb-ch/cb20 befindet sich auch ein EEROS Testprogramm für diese Konfiguration. Mit Hilfe der Skripte werden zuerst die notwendigen Repositories geholt (//clone.sh//). Achtung: im File //config.sh.in// muss für eine Crossentwicklung das notwendige Toolchainfile angegeben werden. Dann kann mit //make.sh// alles übersetzt werden. Anschliessend muss auf das cb20 copiert werden. \\ | + | There is a test program using [[http://eeros.org|EEROS]] under [[https://gitlab.ost.ch/tech/inf/public/cb20]] for the above standard configuration. Use the steps described in [[https://wiki.eeros.org/getting_started/install/use_with_cb20]] to fetch all necessary repositories and build the application. The application reads the suitable hardware configuration file // |
| - | Das Testprogramm liest eine passende Hardware-Konfiguration ein. | + | There is a second application // |
| - | * HwConfigCb20.json: alle Pins werden konfiguriert. Auf den analogen Ausgängen, den digitalen Ausgängen und den PWM-Ausgängen werden Werte ausgegeben. Die Encoder-Eingänge werden geloggt. | + | |
| - | | + | |
| ==== FPGA Design with Watchdog and PPWA ==== | ==== FPGA Design with Watchdog and PPWA ==== | ||
| Zeile 79: | Zeile 77: | ||
| | Dig I/O | 0x12705002 | 6 | 8 | | | | Dig I/O | 0x12705002 | 6 | 8 | | | ||
| | Dig I/O (Enable/ | | Dig I/O (Enable/ | ||
| - | The pins are assigned as with the standard configuration with the following exceptions: P11 has 4 PWM channels | + | The pins are assigned as with the standard configuration with the following exceptions: P11 has 4 PWM channels |
| ==== FPGA Design with MPU9250 ==== | ==== FPGA Design with MPU9250 ==== | ||
| - | This design incorporates a SPI Connection | + | This design incorporates a SPI connection |
| ^ flink component ^ unique id ^ id ^ nof channels ^ description ^ | ^ flink component ^ unique id ^ id ^ nof channels ^ description ^ | ||
| | PWM | 0x1270C001 | 0 | 4 | | | | PWM | 0x1270C001 | 0 | 4 | | | ||