Infoportal
Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
| Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
| embedded_systems:zynq7000:mapping_flink1 [2020-12-01 11:14] – Urs Graf | embedded_systems:zynq7000:mapping_flink1 [2021-11-05 11:46] (aktuell) – Urs Graf | ||
|---|---|---|---|
| Zeile 1: | Zeile 1: | ||
| - | ====== Pin Mapping for flink1-bit Configuration ====== | + | ====== Pin Mapping for flink1 Configuration ====== |
| - | ^FPGA pin^flink device^channel number^ | + | |
| + | |||
| + | <WRAP blindtable 100%> | ||
| + | <WRAP blindcell 30%> | ||
| + | |||
| + | ^FPGA Pin^Flink Device^Flink Channel^ | ||
| |B19|gpio|0| | |B19|gpio|0| | ||
| |B20|:::|1| | |B20|:::|1| | ||
| Zeile 9: | Zeile 14: | ||
| |E19|:::|6| | |E19|:::|6| | ||
| |F17|:::|7| | |F17|:::|7| | ||
| + | |L19|:::|8| | ||
| + | |M19|:::|9| | ||
| + | |L20|::: | ||
| + | |M20|::: | ||
| + | |M17|::: | ||
| + | |K19|::: | ||
| + | |M18|::: | ||
| + | |J19|::: | ||
| + | |L16|::: | ||
| + | |K17|::: | ||
| + | |L17|::: | ||
| + | |K18|::: | ||
| + | |H16|::: | ||
| + | |J18|::: | ||
| + | |H17|::: | ||
| + | |H18|::: | ||
| + | |G17|::: | ||
| + | |F19|::: | ||
| + | |G18|::: | ||
| + | |F20|::: | ||
| + | |G19|::: | ||
| + | |J20|::: | ||
| + | |G20|::: | ||
| + | |H20|::: | ||
| + | |K14|::: | ||
| + | |||
| + | </ | ||
| + | <WRAP blindcell 30%> | ||
| + | |||
| + | ^FPGA Pin^Flink Device^Flink Channel^ | ||
| + | |H15|GPIO|33| | ||
| + | |J14|::: | ||
| + | |G15|::: | ||
| + | |N15|::: | ||
| + | |L14|::: | ||
| + | |N16|::: | ||
| + | |L15|::: | ||
| + | |M14|::: | ||
| + | |K16|::: | ||
| + | |M15|::: | ||
| + | |J16|::: | ||
| + | |V18|::: | ||
| + | |W19|::: | ||
| + | |N17|::: | ||
| + | |P15|::: | ||
| + | |P18|::: | ||
| + | |Y19|::: | ||
| + | |W16|::: | ||
| + | |R16|::: | ||
| + | |T17|::: | ||
| + | |R17|::: | ||
| + | |R18|::: | ||
| + | |V17|::: | ||
| + | |W18|::: | ||
| + | |P19|::: | ||
| + | |P20|::: | ||
| + | |T20|::: | ||
| + | |V20|::: | ||
| + | |U20|::: | ||
| + | |W20|::: | ||
| + | |Y18|::: | ||
| + | |V16|::: | ||
| + | |U17|::: | ||
| + | |||
| + | </ | ||
| + | <WRAP blindcell 30%> | ||
| + | |||
| + | ^FPGA Pin^Flink Device^Flink Channel^ | ||
| + | |W15|GPIO|66| | ||
| + | |U14|::: | ||
| + | |U18|::: | ||
| + | |U15|::: | ||
| + | |U19|::: | ||
| + | |N18|::: | ||
| + | |N20|::: | ||
| + | |T15|::: | ||
| + | |R14|::: | ||
| + | |Y16|::: | ||
| + | |W14|::: | ||
| + | |Y17|::: | ||
| + | |Y14|::: | ||
| + | |T16|::: | ||
| + | |V15|::: | ||
| + | |T10|::: | ||
| + | |U12|::: | ||
| + | |U13|::: | ||
| + | |V12|::: | ||
| + | |V13|::: | ||
| + | |W13|::: | ||
| + | |T14|::: | ||
| + | |P14|::: | ||
| + | |||
| + | ^FPGA Pin^Flink Device^ADC Pin^ | ||
| + | |T11|ADC128S102|DIN| | ||
| + | |T19|::: | ||
| + | |R19|::: | ||
| + | |T12|::: | ||
| + | |||
| + | ^FPGA Pin^Flink Device^ADC Pin^ | ||
| + | |D20|AD7476|SCLK| | ||
| + | |F16|::: | ||
| + | |E18|::: | ||
| + | |||
| + | </ | ||
| + | </ | ||
| + | |||
| + | |||