Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
embedded_systems:zynq7000:mapping_flink1 [2020-12-09 09:30] – Urs Graf | embedded_systems:zynq7000:mapping_flink1 [2021-11-05 11:46] (aktuell) – Urs Graf | ||
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Zeile 1: | Zeile 1: | ||
====== Pin Mapping for flink1 Configuration ====== | ====== Pin Mapping for flink1 Configuration ====== | ||
- | ^FPGA pin^flink device^channel number^ | + | |
+ | |||
+ | <WRAP blindtable 100%> | ||
+ | <WRAP blindcell 30%> | ||
+ | |||
+ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
|B19|gpio|0| | |B19|gpio|0| | ||
|B20|:::|1| | |B20|:::|1| | ||
Zeile 9: | Zeile 14: | ||
|E19|:::|6| | |E19|:::|6| | ||
|F17|:::|7| | |F17|:::|7| | ||
- | |L19|:::|7| | + | |L19|:::|8| |
- | |M19|:::|7| | + | |M19|:::|9| |
- | |L20|:::|7| | + | |L20|:::|10| |
- | |M20|:::|7| | + | |M20|:::|11| |
- | |M17|:::|7| | + | |M17|:::|12| |
- | |K19|:::|7| | + | |K19|:::|13| |
- | |M18|:::|7| | + | |M18|:::|14| |
- | |J19|:::|7| | + | |J19|:::|15| |
- | |L16|:::|7| | + | |L16|:::|16| |
- | |K17|:::|7| | + | |K17|:::|17| |
- | |L17|:::|7| | + | |L17|:::|18| |
- | |K18|:::|7| | + | |K18|:::|19| |
- | |H16|:::|7| | + | |H16|:::|20| |
- | |J18|:::|7| | + | |J18|:::|21| |
- | |H17|:::|7| | + | |H17|:::|22| |
- | |H18|:::|7| | + | |H18|:::|23| |
- | |G17|:::|7| | + | |G17|:::|24| |
- | |F19|:::|7| | + | |F19|:::|25| |
- | |G18|:::|7| | + | |G18|:::|26| |
- | |F20|:::|7| | + | |F20|:::|27| |
- | |G19|:::|7| | + | |G19|:::|28| |
- | |J20|:::|7| | + | |J20|:::|29| |
- | |G20|:::|7| | + | |G20|:::|30| |
- | |H20|:::|7| | + | |H20|:::|31| |
- | |K14|:::|7| | + | |K14|:::|32| |
+ | |||
+ | </ | ||
+ | <WRAP blindcell 30%> | ||
+ | |||
+ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
+ | |H15|GPIO|33| | ||
+ | |J14|::: | ||
+ | |G15|::: | ||
+ | |N15|::: | ||
+ | |L14|::: | ||
+ | |N16|::: | ||
+ | |L15|::: | ||
+ | |M14|::: | ||
+ | |K16|::: | ||
+ | |M15|::: | ||
+ | |J16|::: | ||
+ | |V18|::: | ||
+ | |W19|::: | ||
+ | |N17|::: | ||
+ | |P15|::: | ||
+ | |P18|::: | ||
+ | |Y19|::: | ||
+ | |W16|::: | ||
+ | |R16|::: | ||
+ | |T17|::: | ||
+ | |R17|::: | ||
+ | |R18|::: | ||
+ | |V17|::: | ||
+ | |W18|::: | ||
+ | |P19|::: | ||
+ | |P20|::: | ||
+ | |T20|::: | ||
+ | |V20|::: | ||
+ | |U20|::: | ||
+ | |W20|::: | ||
+ | |Y18|::: | ||
+ | |V16|::: | ||
+ | |U17|::: | ||
+ | |||
+ | </ | ||
+ | <WRAP blindcell 30%> | ||
+ | |||
+ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
+ | |W15|GPIO|66| | ||
+ | |U14|::: | ||
+ | |U18|::: | ||
+ | |U15|::: | ||
+ | |U19|::: | ||
+ | |N18|::: | ||
+ | |N20|::: | ||
+ | |T15|::: | ||
+ | |R14|::: | ||
+ | |Y16|::: | ||
+ | |W14|::: | ||
+ | |Y17|::: | ||
+ | |Y14|::: | ||
+ | |T16|::: | ||
+ | |V15|::: | ||
+ | |T10|::: | ||
+ | |U12|::: | ||
+ | |U13|::: | ||
+ | |V12|::: | ||
+ | |V13|::: | ||
+ | |W13|::: | ||
+ | |T14|::: | ||
+ | |P14|::: | ||
+ | |||
+ | ^FPGA Pin^Flink Device^ADC Pin^ | ||
+ | |T11|ADC128S102|DIN| | ||
+ | |T19|::: | ||
+ | |R19|::: | ||
+ | |T12|::: | ||
+ | |||
+ | ^FPGA Pin^Flink Device^ADC Pin^ | ||
+ | |D20|AD7476|SCLK| | ||
+ | |F16|::: | ||
+ | |E18|::: | ||
+ | |||
+ | </ | ||
+ | </ | ||