Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
embedded_systems:zynq7000:mapping_flink1 [2020-12-09 09:33] – Urs Graf | embedded_systems:zynq7000:mapping_flink1 [2021-11-05 11:46] (aktuell) – Urs Graf | ||
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Zeile 1: | Zeile 1: | ||
====== Pin Mapping for flink1 Configuration ====== | ====== Pin Mapping for flink1 Configuration ====== | ||
- | ^FPGA pin^flink device^channel number^FPGA pin^flink device^channel number^ | + | |
+ | |||
+ | <WRAP blindtable 100%> | ||
+ | <WRAP blindcell 30%> | ||
+ | |||
+ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
|B19|gpio|0| | |B19|gpio|0| | ||
|B20|:::|1| | |B20|:::|1| | ||
Zeile 34: | Zeile 39: | ||
|H20|::: | |H20|::: | ||
|K14|::: | |K14|::: | ||
+ | |||
+ | </ | ||
+ | <WRAP blindcell 30%> | ||
+ | |||
+ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
+ | |H15|GPIO|33| | ||
+ | |J14|::: | ||
+ | |G15|::: | ||
+ | |N15|::: | ||
+ | |L14|::: | ||
+ | |N16|::: | ||
+ | |L15|::: | ||
+ | |M14|::: | ||
+ | |K16|::: | ||
+ | |M15|::: | ||
+ | |J16|::: | ||
+ | |V18|::: | ||
+ | |W19|::: | ||
+ | |N17|::: | ||
+ | |P15|::: | ||
+ | |P18|::: | ||
+ | |Y19|::: | ||
+ | |W16|::: | ||
+ | |R16|::: | ||
+ | |T17|::: | ||
+ | |R17|::: | ||
+ | |R18|::: | ||
+ | |V17|::: | ||
+ | |W18|::: | ||
+ | |P19|::: | ||
+ | |P20|::: | ||
+ | |T20|::: | ||
+ | |V20|::: | ||
+ | |U20|::: | ||
+ | |W20|::: | ||
+ | |Y18|::: | ||
+ | |V16|::: | ||
+ | |U17|::: | ||
+ | |||
+ | </ | ||
+ | <WRAP blindcell 30%> | ||
+ | |||
+ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
+ | |W15|GPIO|66| | ||
+ | |U14|::: | ||
+ | |U18|::: | ||
+ | |U15|::: | ||
+ | |U19|::: | ||
+ | |N18|::: | ||
+ | |N20|::: | ||
+ | |T15|::: | ||
+ | |R14|::: | ||
+ | |Y16|::: | ||
+ | |W14|::: | ||
+ | |Y17|::: | ||
+ | |Y14|::: | ||
+ | |T16|::: | ||
+ | |V15|::: | ||
+ | |T10|::: | ||
+ | |U12|::: | ||
+ | |U13|::: | ||
+ | |V12|::: | ||
+ | |V13|::: | ||
+ | |W13|::: | ||
+ | |T14|::: | ||
+ | |P14|::: | ||
+ | |||
+ | ^FPGA Pin^Flink Device^ADC Pin^ | ||
+ | |T11|ADC128S102|DIN| | ||
+ | |T19|::: | ||
+ | |R19|::: | ||
+ | |T12|::: | ||
+ | |||
+ | ^FPGA Pin^Flink Device^ADC Pin^ | ||
+ | |D20|AD7476|SCLK| | ||
+ | |F16|::: | ||
+ | |E18|::: | ||
+ | |||
+ | </ | ||
+ | </ | ||
+ | |||