Infoportal
Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
| Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
| embedded_systems:zynq7000:mapping_flink1 [2021-09-24 15:06] – Laszlo Arato | embedded_systems:zynq7000:mapping_flink1 [2021-11-05 11:46] (aktuell) – Urs Graf | ||
|---|---|---|---|
| Zeile 1: | Zeile 1: | ||
| ====== Pin Mapping for flink1 Configuration ====== | ====== Pin Mapping for flink1 Configuration ====== | ||
| - | {{: | ||
| <WRAP blindtable 100%> | <WRAP blindtable 100%> | ||
| <WRAP blindcell 30%> | <WRAP blindcell 30%> | ||
| - | ^FPGA pin^flink device^channel number^ | + | ^FPGA Pin^Flink Device^Flink Channel^ |
| |B19|gpio|0| | |B19|gpio|0| | ||
| |B20|:::|1| | |B20|:::|1| | ||
| Zeile 44: | Zeile 43: | ||
| <WRAP blindcell 30%> | <WRAP blindcell 30%> | ||
| - | ^FPGA pin^flink device^channel number^ | + | ^FPGA Pin^Flink Device^Flink Channel^ |
| - | |H15|gpio|33| | + | |H15|GPIO|33| |
| |J14|::: | |J14|::: | ||
| |G15|::: | |G15|::: | ||
| Zeile 82: | Zeile 81: | ||
| <WRAP blindcell 30%> | <WRAP blindcell 30%> | ||
| - | ^FPGA pin^flink device^channel number^ | + | ^FPGA Pin^Flink Device^Flink Channel^ |
| - | |W15|gpio|66| | + | |W15|GPIO|66| |
| |U14|::: | |U14|::: | ||
| |U18|::: | |U18|::: | ||
| Zeile 106: | Zeile 105: | ||
| |T14|::: | |T14|::: | ||
| |P14|::: | |P14|::: | ||
| + | |||
| + | ^FPGA Pin^Flink Device^ADC Pin^ | ||
| |T11|ADC128S102|DIN| | |T11|ADC128S102|DIN| | ||
| |T19|::: | |T19|::: | ||
| |R19|::: | |R19|::: | ||
| |T12|::: | |T12|::: | ||
| + | |||
| + | ^FPGA Pin^Flink Device^ADC Pin^ | ||
| |D20|AD7476|SCLK| | |D20|AD7476|SCLK| | ||
| |F16|::: | |F16|::: | ||
| Zeile 116: | Zeile 119: | ||
| </ | </ | ||
| </ | </ | ||
| + | |||
| + | |||