Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
| Beide Seiten der vorigen RevisionVorhergehende Überarbeitung | |||
| embedded_systems:zynq7000:mapping_flink3 [2021-10-01 11:14] – gelöscht Laszlo Arato | embedded_systems:zynq7000:mapping_flink3 [2021-10-01 12:08] (aktuell) – angelegt Urs Graf | ||
|---|---|---|---|
| Zeile 1: | Zeile 1: | ||
| + | ====== Pin Mapping for flink3 Configuration ====== | ||
| + | |||
| + | <WRAP blindtable 100%> | ||
| + | <WRAP blindcell 30%> | ||
| + | |||
| + | ^FPGA Pin^Flink Device^Flink Channel^ | ||
| + | |N18|gpio|0| | ||
| + | |U15|:::|1| | ||
| + | |U19|:::|2| | ||
| + | |N20|:::|3| | ||
| + | |||
| + | </ | ||
| + | <WRAP blindcell 30%> | ||
| + | |||
| + | ^FPGA Pin^Flink Device^ADC Pin^ | ||
| + | |D18|ADC128S102|DIN| | ||
| + | |M15|::: | ||
| + | |M14|::: | ||
| + | |E17|::: | ||
| + | |||
| + | </ | ||
| + | <WRAP blindcell 30%> | ||
| + | |||
| + | ^FPGA Pin^Flink Device^ADC Pin^ | ||
| + | |B19|AD5668|SCLK| | ||
| + | |D19|::: | ||
| + | |A20|::: | ||
| + | |D20|::: | ||
| + | |F16|::: | ||
| + | |||
| + | </ | ||
| + | </ | ||
| + | |||