Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
Nächste Überarbeitung | Vorhergehende Überarbeitung | ||
embedded_systems:zynq7000:mapping_flink3 [2021-09-29 16:56] – angelegt Laszlo Arato | embedded_systems:zynq7000:mapping_flink3 [2021-10-01 12:08] (aktuell) – angelegt Urs Graf | ||
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Zeile 1: | Zeile 1: | ||
====== Pin Mapping for flink3 Configuration ====== | ====== Pin Mapping for flink3 Configuration ====== | ||
- | |||
- | {{: | ||
<WRAP blindtable 100%> | <WRAP blindtable 100%> | ||
Zeile 7: | Zeile 5: | ||
^FPGA Pin^Flink Device^Flink Channel^ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
- | |B19|GPIO|0| | + | |N18|gpio|0| |
- | |B20|:::|1| | + | |U15|:::|1| |
- | |A20|:::|2| | + | |U19|:::|2| |
- | |E17|:::|3| | + | |N20|:::|3| |
- | |D19|::: | + | |
- | |D18|::: | + | |
- | |E19|::: | + | |
- | |F17|::: | + | |
- | |L19|::: | + | |
- | |M19|::: | + | |
- | |L20|::: | + | |
- | |M20|::: | + | |
- | |M17|::: | + | |
- | |K19|::: | + | |
- | |M18|::: | + | |
- | |J19|::: | + | |
- | |L16|::: | + | |
- | |K17|::: | + | |
- | |L17|::: | + | |
- | |K18|::: | + | |
- | |H16|::: | + | |
- | |J18|::: | + | |
- | |H17|::: | + | |
- | |H18|::: | + | |
- | |G17|::: | + | |
- | |F19|::: | + | |
- | |G18|::: | + | |
- | |F20|::: | + | |
- | |G19|::: | + | |
- | |J20|::: | + | |
- | |G20|::: | + | |
- | |H20|::: | + | |
- | |K14|::: | + | |
- | |H15|GPIO|33| | + | |
- | |J14|::: | + | |
- | |G15|:::|35| | + | |
</ | </ | ||
<WRAP blindcell 30%> | <WRAP blindcell 30%> | ||
- | ^FPGA Pin^Flink Device^Flink Channel^ | + | ^FPGA Pin^Flink Device^ADC Pin^ |
- | |T10|PWM|0| | + | |D18|ADC128S102|DIN| |
- | |U12|::: | + | |M15|:::|SCLK| |
- | |U13|::: | + | |M14|:::|CS| |
- | |V12|::: | + | |E17|:::|DOUT| |
- | |V13|::: | + | |
- | |W13|::: | + | |
- | |T14|::: | + | |
- | |P14|::: | + | |
- | |T15|::: | + | |
- | |R14|::: | + | |
- | |Y16|::: | + | |
- | |W14|::: | + | |
- | |Y17|::: | + | |
- | |Y14|::: | + | |
- | |T16|::: | + | |
- | |V15|::: | + | |
- | |U17|::: | + | |
- | |W15|::: | + | |
- | |U14|::: | + | |
- | |U18|::: | + | |
- | |U15|::: | + | |
- | |U19|::: | + | |
- | |N18|::: | + | |
- | |N20|::: | + | |
- | + | ||
- | ^FPGA Pin^Flink Device^Flink Channel^ | + | |
- | |N15|PPWA|0| | + | |
- | |L14|:::|1| | + | |
- | |N16|::: | + | |
- | |L15|:::|3| | + | |
- | |M14|:::|4| | + | |
- | |K16|::: | + | |
- | + | ||
- | ^FPGA Pin^Flink Device^Flink Channel^ | + | |
- | |V18|UART|TX[0]| | + | |
- | |W19|::: | + | |
- | |N17|::: | + | |
- | |P15|:::|RX[1]| | + | |
</ | </ | ||
<WRAP blindcell 30%> | <WRAP blindcell 30%> | ||
- | |||
- | ^FPGA Pin^Flink Device^Function^ | ||
- | |M15|Watchdog|PWM| | ||
- | |J16|Watchdog|Granted| | ||
- | |||
- | ^FPGA Pin^Flink Device^Flink Channel^ | ||
- | |P19|FQD|0[A]| | ||
- | |P20|::: | ||
- | |T20|::: | ||
- | |V20|::: | ||
- | |U20|::: | ||
- | |W20|::: | ||
- | |Y18|::: | ||
- | |V16|::: | ||
- | |Y19|::: | ||
- | |W16|::: | ||
- | |R16|::: | ||
- | |T17|::: | ||
- | |R17|::: | ||
- | |R18|::: | ||
- | |V17|::: | ||
- | |W18|::: | ||
- | |||
- | ^FPGA Pin^Flink Device^ADC Pin^ | ||
- | |T11|ADC128S102|DIN| | ||
- | |T19|::: | ||
- | |R19|::: | ||
- | |T12|::: | ||
^FPGA Pin^Flink Device^ADC Pin^ | ^FPGA Pin^Flink Device^ADC Pin^ | ||
- | |D20|AD7476|SCLK| | + | |B19|AD5668|SCLK| |
- | |F16|:::|CS| | + | |D19|:::|SYNC| |
- | |E18|:::|DATA| | + | |A20|::: |
+ | |D20|::: | ||
+ | |F16|:::|CLR| | ||
</ | </ |