https://wiki.bu.ost.ch/infoportal/ 2026-05-12T20:05:08+00:00 https://wiki.bu.ost.ch/infoportal/ https://wiki.bu.ost.ch/infoportal/lib/tpl/ntb2/images/favicon.ico text/html 2023-03-23T09:49:00+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.bu.ost.ch/infoportal/embedded_systems/zynq7000/carrier?rev=1679561340&do=diff Carrier Card Design Some of the pins of the board are dedicated to a predefined function, some of the pins can be assigned a desired function. This assignment is made within the kernel of your operating system or dependent software drivers. Please check text/html 2019-04-26T09:14:50+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.bu.ost.ch/infoportal/embedded_systems/zynq7000/jtag?rev=1556262890&do=diff Debugging mit JTAG Einleitung Das Zybo hat eine eingebaute FTDI FT2232HQ USB-UART Bridge, die für JTAG und eine UART Verbindung genutzt wird. Zusätzlich hat es einen unbestückten JTAG Port, der Beispielsweise mit dem BDI3000 genutzt werden kann. text/html 2021-11-05T11:46:05+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.bu.ost.ch/infoportal/embedded_systems/zynq7000/mapping_flink1?rev=1636109165&do=diff Pin Mapping for flink1 Configuration FPGA PinFlink DeviceFlink ChannelB19gpio0B201A202E173D194D185E196F177L198M199L2010M2011M1712K1913M1814J1915L1616K1717L1718K1819H1620J1821H1722H1823G1724F1925G1826F2027G1928J2029G2030H2031K1432FPGA PinFlink DeviceFlink Channel text/html 2024-01-05T09:50:27+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.bu.ost.ch/infoportal/embedded_systems/zynq7000/mapping_flink2?rev=1704444627&do=diff Pin Mapping for flink2 Configuration FPGA PinFlink DeviceFlink ChannelM17GPIO0K191M182J193L164K175L176K187H168J189H1710H1811G1712F1913G1814F2015G1916J2017G2018H2019K1420H1521J1422G1523FPGA PinFlink DeviceFlink ChannelN15PPWA0FPGA PinFlink DeviceFunction text/html 2021-10-01T12:08:27+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.bu.ost.ch/infoportal/embedded_systems/zynq7000/mapping_flink3?rev=1633082907&do=diff Pin Mapping for flink3 Configuration FPGA PinFlink DeviceFlink ChannelN18gpio0U151U192N203FPGA PinFlink DeviceADC PinD18ADC128S102DINM15SCLKM14CSE17DOUTFPGA PinFlink DeviceADC PinB19AD5668SCLKD19SYNCA20DIND20LDACF16CLR text/html 2021-12-07T09:33:58+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.bu.ost.ch/infoportal/embedded_systems/zynq7000/mapping_flink4?rev=1638866038&do=diff Pin Mapping for flink4 Configuration FPGA PinFlink DeviceFlink ChannelN18FQD0[A]U150[B]U191[A]N201[B]FPGA PinFlink DeviceADC PinD18ADC128S102DINM15SCLKM14CSE17DOUTFPGA PinFlink DeviceADC PinB19AD5668SCLKD19SYNCA20DIND20LDACF16CLR text/html 2021-10-01T14:07:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.bu.ost.ch/infoportal/embedded_systems/zynq7000/mapping_new_flink2?rev=1633090066&do=diff Pin Mapping for NEW Flink2 Configuration FPGA PinFlink DeviceFlink ChannelG14GPIO0J151B192A203D194E195F176M177K198M189J1910L1611K1712L1713K1814H1615H1716G1717F1918G1819F2020G1921G2022H1523G1524Y1225V1126Y1327V1028V629W630V531U732T933V734U1035V836T5 text/html 2023-12-01T16:40:09+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.bu.ost.ch/infoportal/embedded_systems/zynq7000/microzed?rev=1701445209&do=diff MicroZed Board The MicroZed contains a Zynq7000 SOC and lots of peripherals. Key Features * XC7Z010-1CLG400C * 33.33 MHz oscillator * 1 GB of DDR3 SDRAM * 128 Mb of QSPI Flash * Micro SD card interface * 10/100/1000 Ethernet * USB 2.0 * USB-UART text/html 2022-06-03T14:48:51+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.bu.ost.ch/infoportal/embedded_systems/zynq7000/rtboard?rev=1654260531&do=diff RT-Board Das RT-Board (RegelungsTechnik-Board) eignet sich als Plattform für kleine Steuerungen. Die Kernkomponente ist ein Zynq7000. Features * 4 digitale Ein- und Ausgänge als 4 mm Buchsen * 2 analoge Ausgänge (±10 V) als 4 mm Buchsen * 2 analoge Leistungsausgänge (±10 V, 2A) als 4 mm Buchsen text/html 2022-03-02T09:05:31+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.bu.ost.ch/infoportal/embedded_systems/zynq7000/start?rev=1646208331&do=diff Zynq7000 The Zynq7000 integrates a single or dual core Cortex-A9 MPCore processor together with a Xilinx FPGA. Manual * [Zynq 7000 Technical reference manual] * ARM Cortex-A9 MPCore * [Pinout for Zynq7000 ] * [XADC LogiCORE IP] Boards * ZYBO * MicroZed * RT-Board Software * Xilinx SDK Weitere Unterlagen * [Software developers guide] text/html 2021-03-16T08:38:14+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.bu.ost.ch/infoportal/embedded_systems/zynq7000/xsdk?rev=1615880294&do=diff Xilinx SDK Installation Note: A Xilinx account is required! Standalone SDK installation * Download the SDK 2019.1 web installer from here: <https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis/archive-sdk.html> After a successful download start the installer. * Continue: * Next: * Insert your Xilinx account credentials, select text/html 2019-12-03T09:30:40+00:00 Anonymous (anonymous@undisclosed.example.com) https://wiki.bu.ost.ch/infoportal/embedded_systems/zynq7000/zybo?rev=1575361840&do=diff ZYBO Board The ZYBO contains a Zynq7000 SOC and lots of peripherals. Manuals * [Zybo Board Reference Manual] * [Zybo Schematic] * [Zynq 7000 Datasheet] Further Documents * Sehr gutes Einsteiger Tutorial. Für das Tutorial wird Vivado (im NTB-Kiosk erhältlich) und das XSDK (Xilinx SDK) benötigt. * Debugging mit JTAG