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Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
| Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
| software:flink:flink_vhdl [2015-02-04 16:31] – graf | software:flink:flink_vhdl [Unbekanntes Datum] (aktuell) – gelöscht - Externe Bearbeitung (Unbekanntes Datum) 127.0.0.1 | ||
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| - | ====== VHDL ====== | ||
| - | <box blue right 38% | **Downloads**> | ||
| - | * [[https:// | ||
| - | </ | ||
| - | This is the user documentation for the flink VHDL modules. At the current state flink is only available for Altera FPGAs. | ||
| - | |||
| - | ===== Overview ===== | ||
| - | <box green right 38% | **Functions**> | ||
| - | * [[.: | ||
| - | </ | ||
| - | ===== Requirements ===== | ||
| - | * Quartus Version 13.0.1 Service Pack 1 together with Qsys 13.0sp1 | ||
| - | * Modelsim Altera 10.1d (only necessary for simulation of modules) | ||
| - | |||
| - | ===== Building ===== | ||
| - | - Start Quartus and create a new project. | ||
| - | - Choose your appropriate device. | ||
| - | - Under //Device -> Device and Pin Options... -> Unused Pins// choose //As input tri-stated with weak pull-up//. Without this setting the system will not work later! | ||
| - | - Start Qsys and choose //Tools -> Options//. Press //Add// and choose the fLink repository root path. After pressing //Finish// flink should be listed in the library section. | ||
| - | - Add all your desired modules to your system by double clicking on the appropriate entry. Also add an interface module such as a PCI or SPI interface. | ||
| - | - Connect all the clock sinks as well as the reset sinks. | ||
| - | - Connect the avalon master interface of the interface module with the avalon slave interfaces of all the other modules. | ||
| - | - In the export column double click on the conduit part of every module. | ||
| - | - Choose // | ||
| - | - Select the tab // | ||
| - | - Close Qsys and change to the //Files// tab in the project view in Quartus. Add the .qip file from the synthesis folder of the Qsys system. | ||
| - | - Set the .qip file as // | ||
| - | - Select //Analyse and Synthesis// | ||
| - | - Open Pin Planer and designate all the necessary pins. | ||
| - | - Compile the design and download it. | ||