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--- software:flink:flink_vhdl [2015-02-11 13:11] – tinner
+++ software:flink:flink_vhdl [Unbekanntes Datum] (aktuell) – gelöscht - Externe Bearbeitung (Unbekanntes Datum) 127.0.0.1
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-====== VHDL ======
-<box blue right 38% | **Downloads**>
-  * [[https://github.com/flink-project/flinkvhdl | flink VHDL Modules on Github]]
-</box>
-This is the user documentation for the flink VHDL modules. At the current state flink is only available for Altera FPGAs.
-===== Overview =====
-<box green right 38% | **Functions**>
-  * [[.:subdevices|Available functions]]
-</box>
-===== Requirements =====
-  * Quartus Version 13.0.1 Service Pack 1 together with Qsys 13.0sp1
-  * Modelsim Altera 10.1d (only necessary for simulation of modules)
-===== Building =====
-  - Start Quartus and create a new project.
-  - Choose your appropriate device.
-  - Under //Device -> Device and Pin Options... -> Unused Pins// choose //As input tri-stated with weak pull-up//. Without this setting the system will not work later!
-  - Start Qsys and choose //Tools -> Options//. Press //Add// and choose the fLink repository root path. After pressing //Finish// flink should be listed in the library section.
-  - Add all your desired subdevices to your system by double clicking on the appropriate entry. Set all the necessary parameters, among them ''unique_id''.  Also add an interface module such as a PCI or SPI interface.
-  - Add a info subdevice if necessary. An info subdevice can be very useful for reading the total memory size of the whole device as well as reading the description field. This can be used to cross check whether the right design is loaded in the FPGA.
-  - Connect all the clock sinks as well as the reset sinks.
-  - Connect the avalon master interface of the interface module with the avalon slave interfaces of all the other subdevices.
-  - In the export column double click on the conduit part of every subdevice.
-  - Choose //System->Assign Base Addresses//. Make sure that there are no empty spaces between subsequent subdevices.
-  - Select the tab //Generation Writer// on the top and choose VHDL in the Synthesis part. Save the system and click the //Generate// button.
-  - Close Qsys and change to the //Files// tab in the project view in Quartus. Add the .qip file from the synthesis folder of the Qsys system.
-  - Set the .qip file as //Top-Level-Entity//.
-  - Select //Analyse and Synthesis//.
-  - Open Pin Planer and designate all the necessary pins.
-  - Compile the design and download it.
-===== Id and Unique_Id =====
-Every subdevice has a parameter ''unique_id''. The user can assign any unique value to it. Please keep a list with these values.\\
-When a flink device is later scanned and all its contained subdevices read out, every subdevice is numbered with numbers starting from 0. This number is the ''id''. A subdevice can now be selected either by its ''unique_id'' or its ''id''. \\
-The ''unique_id'' is defined as a parameter when configuring the subdevice in the FPGA. On the other side, ''id'' is set at runtime when subdevices are scanned. ''id'' therefore depends on the arrangement of the subdevices in a device. ''unique_id'' can be kept constant in any arrangement. \\
-An userland application should use ''unique_id'' when searching for a subdevice. This ensures that the application doesn't have to be recompiled when more subdevices are added to a FPGA design and the memory arrangement changes.
-===== Info Subdevice =====
-An info subdevice serves for information purposes only. It comprises the fields ''unique_id'', ''description'' and ''mem_length'' and has no channels. It can be included in any design if desired. ''mem_length'' is very handy if the interface to the FPGA doesn't allow for enumeration. In those cases the info subdevice can be queried for this field.\\
-The field ''description'' can be used to assertain that a specific design is present in the FPGA.

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