This is the user documentation for the flink VHDL modules. At the current state flink is only available for Altera FPGAs.

• Quartus Version 13.0.1 Service Pack 1 together with Qsys 13.0sp1
• Modelsim Altera 10.1d (only necessary for simulation of modules)

1. Start Quartus and create a new project.
2. Choose your appropriate device.
3. Under Device → Device and Pin Options… → Unused Pins choose As input tri-stated with weak pull-up. Without this setting the system will not work later!
4. Start Qsys and choose Tools → Options. Press Add and choose the fLink repository root path. After pressing Finish flink should be listed in the library section.
5. Add all your desired subdevices to your system by double clicking on the appropriate entry. Set all the necessary parameters, among them unique_id. Also add an interface module such as a PCI or SPI interface.
6. Add a info subdevice if necessary. An info subdevice can be very useful for reading the total memory size of the whole device as well as reading the description field. This can be used to cross check whether the right design is loaded in the FPGA.
7. Connect all the clock sinks as well as the reset sinks.
8. Connect the avalon master interface of the interface module with the avalon slave interfaces of all the other subdevices.
9. In the export column double click on the conduit part of every subdevice.
10. Choose System→Assign Base Addresses. If an info subdevice is present, make sure that it sits a address 0.
11. Select the tab Generation Writer on the top and choose VHDL in the Synthesis part. Save the system and click the Generate button.
12. Close Qsys and change to the Files tab in the project view in Quartus. Add the .qip file from the synthesis folder of the Qsys system.
13. Set the .qip file as Top-Level-Entity.
14. Select Analyse and Synthesis.
15. Open Pin Planer and designate all the necessary pins.
16. Compile the design and download it.