Infoportal
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Available Subdevices
The functions given below have so far been implemented as VHDL modules (see VHDL). For all of them a suitable driver is available in the flink Userspace Library
| function id | name | description |
|---|---|---|
| 0x00 | Info | info subdevice with description |
| 0x01 | AnalogIn | analog input, ADC |
| 0x02 | AnalogOut | analog output, DAC, not yet implemented |
| 0x05 | DigitalIO | digital inputs and outputs, GPIO |
| 0x06 | Counter | counters |
| 0x0c | PWM | pulse width modulated outputs |
| 0x10 | Watchdog | watchdog timers |
Subdevice Specific Registers
As described in flink, Universal Serial Interface to FPGA's every subdevice realizes a certain function. The function id together with status and configuration registers can be found in the header and subheader section. Every subdevice has further registers which are specific for a certain function. These registers are described below for the available functions.
Info Subdevice
This subdevice might be present or not in a device. Its purpose is to indicate the total memory size of the whole device. It further has a 28 bytes description field. This allows for identifying a given design.
| Offset | Size [byte] | Name | r/w | Const | Description |
|---|---|---|---|---|---|
| 0x20 | 4 | memory size | r | yes | total memory size for the device (in bytes) including all subdevices |
| 0x24 | 28 | description | r | yes | contains a description, including a name and/or a date |
The status and configuration registers in the subheader are unused with this function.
ADC
| Offset | Size [byte] | Name | r/w | Const | Description |
|---|---|---|---|---|---|
| 0x20 | 4 | resolution | r | yes | this is the number of resolvable digital steps |
| 0x24 | 4 | value_0 | r | no | channel 0: digitized input value |
| 0x28 | 4 | value_1 | r | no | channel 1: digitized input value |
| .. | 4 | .. | r/w | no | .. |
The status and configuration registers in the subheader are unused with this function.
Subtypes
Currently there are two subtypes of this subdevice
| ID | Description | Example |
|---|---|---|
| 0x1 | Simple ADC with continuous sampling | ADC128S102 |
| 0x2 | Advanced model with integrated filter and sampling mode selection | AD7606 |
DAC
| Offset | Size [byte] | Name | r/w | Const | Description |
|---|---|---|---|---|---|
| 0x20 | 4 | resolution | r | yes | this is the number of resolvable digital steps |
| 0x24 | 4 | value_0 | r/w | no | channel 0: digital output value |
| 0x28 | 4 | value_1 | r/w | no | channel 1: digital output value |
| .. | 4 | .. | r/w | no | .. |
The status and configuration registers in the subheader are unused with this function.
Subtypes
Currently there is one subtypes of this subdevice
| ID | Description | Example |
|---|---|---|
| 0x1 | Simple DAC where the outputs are continuously set. All channels are updated at the same time | AD5668 |
GPIO
| Offset | Size [byte] | Name | r/w | Const | Description |
|---|---|---|---|---|---|
| 0x20 | 4 | dir_0 | r/w | no | direction bits for channels 0 .. 31 |
| 0x24 | 4 | dir_1 | r/w | no | direction bits for channels 32 .. 63 |
| .. | 4 | .. | r/w | no | .. |
| 0xyy | 4 | val_0 | r/w | no | digital value for channels 0 .. 31 |
| 0xyy+4 | 4 | val_1 | r/w | no | digital value for channels 32 .. 63 |
| .. | 4 | .. | r/w | no | .. |
A value of '1' configures a pin as an output in the direction register. The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice.
Counter
All modules which count something can implement this interface. An example for this could be a FQD (fast quadrature decoder). It counts the number of edges of a signal.
| Offset | Size [byte] | Name | r/w | Const | Description |
|---|---|---|---|---|---|
| 0x20 | 4 | count_0 | r | no | counter channel 0 |
| 0x24 | 4 | count_1 | r | no | counter channel 1 |
| .. | 4 | .. | r | no | .. |
PWM
| Offset | Size [byte] | Name | r/w | Const | Description |
|---|---|---|---|---|---|
| 0x20 | 4 | base_clk | r | no | base clock in Hz |
| 0x24 | 4 | ptime_0 | r/w | no | channel 0: period in multiples of base clock |
| 0x28 | 4 | ptime_1 | r/w | no | channel 1: period in multiples of base clock |
| .. | 4 | .. | r/w | no | .. |
| 0xyy | 4 | htime_0 | r/w | no | channel 0: high time in multiples of base clock |
| 0xyy+4 | 4 | htime_1 | r/w | no | channel 1: high time in multiples of base clock |
| .. | 4 | .. | r/w | no | .. |
The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice.
Watchdog
If the counter reaches 0 the watchdog fires and osl_granted goes to '0'. The counter decrements with every clock cycle. Is has to be written periodically to prevent the watchdog of running out.
| Offset | Size [byte] | Name | r/w | Const | Description |
|---|---|---|---|---|---|
| 0x20 | 4 | base_clk | r | yes | base clock in Hz |
| 0x24 | 4 | status_conf | r/w | no | status and configuration register |
| 0x28 | 4 | counter | r/w | no | counter |
status_conf
| 31 | … | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
| rearm | status |
status: shows the value of the osl_granted signal. If '1': the output is set, if '0': the output is not set | rearm: When the watchdog has fired, it has to be reset with this signal. Write '1' to rearm. This bit is self clearing to '0'.