USB-BDI
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This file contains only the SYNCDELAY MACRO. More...
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Defines | |
#define | SYNCDELAY __asm nop; nop; nop; __endasm |
#define | NOP __asm nop; __endasm |
This file contains only the SYNCDELAY MACRO.
Magic delay required between access to certain xdata registers (TRM page 15-106). For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each NOP is a single cycle....
From TRM page 15-105:
Under certain conditions, some read and write access to the FX2 registers must be separated by a "synchronization delay". The delay is necessary only under the following conditions:
Registers which require a synchronization delay:
FIFORESET FIFOPINPOLAR INPKTEND EPxBCH:L EPxFIFOPFH:L EPxAUTOINLENH:L EPxFIFOCFG EPxGPIFFLGSEL PINFLAGSAB PINFLAGSCD EPxFIFOIE EPxFIFOIRQ GPIFIE GPIFIRQ UDMACRCH:L GPIFADRH:L GPIFTRIG EPxGPIFTRIG OUTPKTEND REVCTL GPIFTCB3 GPIFTCB2 GPIFTCB1 GPIFTCB0
Definition in file syncdelay.h.
#define NOP __asm nop; __endasm |
1 times nop
Definition at line 63 of file syncdelay.h.
#define SYNCDELAY __asm nop; nop; nop; __endasm |
3 times nop
Definition at line 61 of file syncdelay.h.