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In a DC system each participant has its own clock which is synchronized with all other clocks. The Sync0 event is triggered synchronously by all participants.
The Sync0 event ist triggered on all devices of the network at the same time. The slaves can read inputs and set outputs after a deterministic and configurable time after the Sync0 event. Thus it is possible that all outputs in the whole network are set simultaneously within nanoseconds. It is also possible to set the outputs with a desired time delay.
In „DCM Master Shift Mode“ the hardware clock of the first slave is used as main clock. All slave clocks as well as the master clock are synchronized with this clock.
The jitter of the master has no direct influence on the jitter of the Sync0 event. However, if the jitter of the master is too high and the period too short, an EC frame may be sent too late. The slaves then do not receive the data sufficiently early before the next Sync0 even is triggeredt.
: corresponding error message
In „DCM Bus Shift Mode“ the clock of the master is used as the main clock. All slaves are synchronized with the clock of the master. The jitter of the master directly influences the jitter of the Sync0 event.
After the Sync0 event, the received data from the Ethernet driver are first copied into the buffer of the Acontis stack on the master. Then the application can evaluate the received data and set the outputs. As soon as the cyclic job of the application is completed, the EC Frame is sent from the stack.
The period between the frames is only deterministic to a limited extent. In this mode only the period between the Sync 0 events is deterministic!
This example shows the flow of a signal through an EtherCAT network.