Infoportal
Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
| Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
| embedded_systems:ethercat:understanding_ethercat:understanding_sync_with_dc [2019-02-08 09:51] – mgehrig2 | embedded_systems:ethercat:understanding_ethercat:understanding_sync_with_dc [2019-02-13 11:32] (aktuell) – mgehrig2 | ||
|---|---|---|---|
| Zeile 7: | Zeile 7: | ||
| ===== The Sync0 Synchronisation Signal ===== | ===== The Sync0 Synchronisation Signal ===== | ||
| In a DC system each participant has its own clock which is synchronized with all other clocks. | In a DC system each participant has its own clock which is synchronized with all other clocks. | ||
| - | The Sync0 event is triggered synchronously | + | The Sync0 event is triggered synchronously |
| ==== The Sync0 Event ==== | ==== The Sync0 Event ==== | ||
| The Sync0 event ist triggered on all devices of the network at the same time. | The Sync0 event ist triggered on all devices of the network at the same time. | ||
| - | The slaves can read inputs and set outputs after a deterministic and configurable time after the Sync0 event. | + | The slaves can read inputs and set outputs after a deterministic and configurable time (1C32:06 + 1C32: |
| Thus it is possible that all outputs in the whole network are set simultaneously within nanoseconds. | Thus it is possible that all outputs in the whole network are set simultaneously within nanoseconds. | ||
| + | The same is true for reading inputs at a determenistic time. | ||
| It is also possible to set the outputs with a desired time delay. | It is also possible to set the outputs with a desired time delay. | ||
| + | |||
| + | {{ : | ||
| ==== DCM Master Shift Mode ==== | ==== DCM Master Shift Mode ==== | ||
| Zeile 23: | Zeile 26: | ||
| The slaves then do not receive the data sufficiently early before the next Sync0 even is triggeredt. | The slaves then do not receive the data sufficiently early before the next Sync0 even is triggeredt. | ||
| - | TODO: corresponding | + | The coresponding |
| + | < | ||
| + | 082039 : eUsrJob_ProcessAllRxFrames - not all previously sent frames are received/ | ||
| + | </ | ||
| ==== DCM Bus Shift Mode ==== | ==== DCM Bus Shift Mode ==== | ||
| Zeile 34: | Zeile 40: | ||
| After the Sync0 event, the received data from the Ethernet driver are first copied into the buffer of the Acontis stack on the master. | After the Sync0 event, the received data from the Ethernet driver are first copied into the buffer of the Acontis stack on the master. | ||
| Then the application can evaluate the received data and set the outputs. | Then the application can evaluate the received data and set the outputs. | ||
| - | As soon as the cyclic job of the application is completed, the EC Frame is sent from the stack. | + | As soon as the cyclic job of the application is completed, the EC Frame is sent from the master to the slaves. |
| + | |||
| + | ==== Cycle time ==== | ||
| + | The cycle time between the EtherCAT frames is only deterministic to a limited extent. | ||
| + | If the application needs in one cycle more time to calculate the results, the frames are sent later than in the cycle before. | ||
| + | |||
| + | The time between two consecutive inputs measurements is very constant, because they are synchronized with the Sync0 event. | ||
| + | The same is true for writing outputs. | ||
| - | The period between | + | For calculations in control applications, |
| - | In this mode only the period between the Sync 0 events is deterministic! | + | |