Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
embedded_systems:zynq7000:carrier [2021-01-21 22:22] – Urs Graf | embedded_systems:zynq7000:carrier [2023-03-23 09:49] (aktuell) – Urs Graf | ||
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====== Carrier Card Design ====== | ====== Carrier Card Design ====== | ||
+ | Some of the pins of the board are dedicated to a predefined function, some of the pins can be assigned a desired function. This assignment is made within the kernel of your operating system or dependent software drivers. Please check [[https:// | ||
+ | |||
===== Supply ===== | ===== Supply ===== | ||
Zeile 5: | Zeile 7: | ||
^Voltage^Signal^Pin^ | ^Voltage^Signal^Pin^ | ||
|5V|5V|JX1 57, 58, 59, 60| | |5V|5V|JX1 57, 58, 59, 60| | ||
- | |3.3V|3.3V_B34|JX1 78, 79, 80| | + | |3.3V|VCCO_B34|JX1 78, 79, 80| |
- | |3.3V|3.3V_B35|JX2 78, 79, 80| | + | |3.3V|VCCO_B35|JX2 78, 79, 80| |
|Gnd|0V|several on JX1 and JX2| | |Gnd|0V|several on JX1 and JX2| | ||
Other necessary voltages (1.0V, 1.8V, 1.5V, 3.3V) are generated directly on the MicroZed board. | Other necessary voltages (1.0V, 1.8V, 1.5V, 3.3V) are generated directly on the MicroZed board. | ||
- | The board will draw approximately 1.2A from the 5V supply. | + | The board will draw approximately 1.2A from the 5V supply. The current drawn on the IO-Bank supplies VCCO_B34 and VCCO_B35 is approximately the sum of all currents on the pins of the two banks. |
===== Reset ===== | ===== Reset ===== | ||
- | The Zynq7000 has a power-on reset pin (PS_POR_B). The corresponding net designator on the MicroZed board is PG_MODULE. The signal is available on J2 (pin 11). Tie this pin to ' | + | The Zynq7000 has a power-on reset pin (PS_POR_B). The corresponding net designator on the MicroZed board is PG_MODULE. The signal is available on J2 (pin 11). Tie this pin to ' |
+ | |||
+ | There is a second reset pin on J1 (pin 6). Tieing this pin to ' | ||
+ | |||
+ | ===== Digital I/O ===== | ||
+ | The electrical specification of the pins of the PL (FPGA part) are determined by IO-Bank supplies 3.3V_B34 and 3.3V_B35, see above. Pins of the MIO (bank 500) are of 3.3V type. Please be aware that all the flink devices such as PWM, FQD or UART have the same voltage levels as regular IO pins. \\ | ||
+ | WARNING For interconnections to other devices such as processors or sensors you have to strictly adhere to the maximum voltage allowed. To be on the safe side we recommend using overvoltage protection with Zener diodes as used on our [[embedded_systems: | ||
===== ADC ===== | ===== ADC ===== | ||
- | The MicroZed board doesn' | + | The Zynq7000 processor incorporates |
+ | and VN) have an input range of 0V to 1.0V. The voltage on VP (measured with | ||
+ | respect to VN) must always be positive. VN is typically connected to a local ground. Because the differential input range is from 0V to 1.0V (VP to VN), the maximum signal on VP is 1.0V. | ||
+ | WARNING For interconnections to other devices such as sensors you have to strictly adhere to the maximum voltage allowed. | ||
+ | |||
+ | You can also connect |