Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
embedded_systems:zynq7000:mapping_flink2 [2021-02-04 22:31] – Urs Graf | embedded_systems:zynq7000:mapping_flink2 [2024-01-05 09:50] (aktuell) – Laszlo Arato | ||
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====== Pin Mapping for flink2 Configuration ====== | ====== Pin Mapping for flink2 Configuration ====== | ||
- | {{: | + | {{: |
- | ^FPGA pin^flink device^channel number^FPGA pin^flink device^channel number^FPGA pin^flink device^channel number^ | + | <WRAP blindtable 100%> |
- | |B19|gpio|0|T10|pwm|0|P19|fqd|0[A]| | + | <WRAP blindcell |
- | |B20|::: | + | |
- | |A20|::: | + | |
- | |E17|::: | + | |
- | |D19|::: | + | |
- | |D18|::: | + | |
- | |E19|::: | + | |
- | |F17|::: | + | |
- | |L19|::: | + | |
- | |M19|::: | + | |
- | |L20|::: | + | |
- | |M20|::: | + | |
- | |M17|::: | + | |
- | |K19|::: | + | |
- | |M18|::: | + | |
- | |J19|::: | + | |
- | |L16|::: | + | |
- | |K17|::: | + | |
- | |L17|::: | + | |
- | |K18|::: | + | |
- | |H16|::: | + | |
- | |J18|::: | + | |
- | |H17|::: | + | |
- | |H18|::: | + | |
- | |G17|::: | + | |
- | |F19|::: | + | |
- | |G18|::: | + | |
- | |F20|::: | + | |
- | |G19|::: | + | |
- | |J20|::: | + | |
- | |G20|:::|30|V18|UART|tx[0]| | + | |
- | |H20|::: | + | |
- | |K14|::: | + | |
- | |H15|::: | + | |
- | |J14|::: | + | |
- | |G15|::: | + | |
+ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
+ | |M17|GPIO|0| | ||
+ | |K19|:::|1| | ||
+ | |M18|:::|2| | ||
+ | |J19|:::|3| | ||
+ | |L16|:::|4| | ||
+ | |K17|:::|5| | ||
+ | |L17|:::|6| | ||
+ | |K18|:::|7| | ||
+ | |H16|:::|8| | ||
+ | |J18|:::|9| | ||
+ | |H17|::: | ||
+ | |H18|::: | ||
+ | |G17|::: | ||
+ | |F19|::: | ||
+ | |G18|::: | ||
+ | |F20|::: | ||
+ | |G19|::: | ||
+ | |J20|::: | ||
+ | |G20|::: | ||
+ | |H20|::: | ||
+ | |K14|::: | ||
+ | |H15|::: | ||
+ | |J14|::: | ||
+ | |G15|::: | ||
+ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
+ | |N15|PPWA|0| | ||
+ | ^FPGA Pin^Flink Device^Function^ | ||
+ | |L14|TCRT1000|Trig| | ||
+ | |N16|::: | ||
+ | |L15|::: | ||
+ | |M14|::: | ||
+ | |K16|::: | ||
+ | |||
+ | </ | ||
+ | <WRAP blindcell 30%> | ||
+ | |||
+ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
+ | |T10|PWM|0| | ||
+ | |U12|:::|1| | ||
+ | |U13|:::|2| | ||
+ | |V12|:::|3| | ||
+ | |V13|:::|4| | ||
+ | |W13|:::|5| | ||
+ | |T14|:::|6| | ||
+ | |P14|:::|7| | ||
+ | |T15|:::|8| | ||
+ | |R14|:::|9| | ||
+ | |Y16|::: | ||
+ | |W14|::: | ||
+ | |Y17|::: | ||
+ | |Y14|::: | ||
+ | |T16|::: | ||
+ | |V15|::: | ||
+ | |U17|::: | ||
+ | |W15|::: | ||
+ | |U14|::: | ||
+ | |U18|::: | ||
+ | |U15|::: | ||
+ | |U19|::: | ||
+ | |N18|::: | ||
+ | |N20|::: | ||
+ | |||
+ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
+ | |V18|UART|TX[0]| | ||
+ | |W19|::: | ||
+ | |N17|::: | ||
+ | |P15|::: | ||
+ | |||
+ | ^FPGA Pin^Flink Device^Function^ | ||
+ | |M15|Watchdog|PWM| | ||
+ | |J16|Watchdog|Granted| | ||
+ | |||
+ | </ | ||
+ | <WRAP blindcell 30%> | ||
+ | |||
+ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
+ | |P19|FQD|0[A]| | ||
+ | |P20|::: | ||
+ | |T20|::: | ||
+ | |V20|::: | ||
+ | |U20|::: | ||
+ | |W20|::: | ||
+ | |Y18|::: | ||
+ | |V16|::: | ||
+ | |Y19|::: | ||
+ | |W16|::: | ||
+ | |R16|::: | ||
+ | |T17|::: | ||
+ | |R17|::: | ||
+ | |R18|::: | ||
+ | |V17|::: | ||
+ | |W18|::: | ||
+ | |||
+ | ^FPGA Pin^Flink Device^ADC Pin^ | ||
+ | |T11|ADC128S102|DIN| | ||
+ | |T19|::: | ||
+ | |R19|::: | ||
+ | |T12|::: | ||
+ | |||
+ | ^FPGA Pin^Flink Device^ADC Pin^ | ||
+ | |D20|AD7476|SCLK| | ||
+ | |F16|::: | ||
+ | |E18|::: | ||
+ | |||
+ | ^FPGA Pin^XADC Device^Channel^ | ||
+ | |E17|XADC|0[p]| | ||
+ | |D18|::: | ||
+ | |M19|::: | ||
+ | |M20|::: | ||
+ | |L19|::: | ||
+ | |L20|::: | ||
+ | |B19|::: | ||
+ | |A20|::: | ||
+ | |||
+ | </ | ||
+ | </ | ||