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Pin Mapping for flink2 Configuration

FPGA pin	flink device	channel number	FPGA pin	flink device	channel number	FPGA pin	flink device	channel number
B19	gpio	0	T10	pwm	0	P19	fqd	0[A]
B20		1	U12		1	P20		0[B]
A20		2	U13		2	T20		1[A]
E17		3	V12		3	V20		1[B]
D19		4	V13		4	U20		2[A]
D18		5	W13		5	W20		2[B]
E19		6	T14		6	Y18		3[A]
F17		7	P14		7	V16		3[B]
L19		8	T15		8	Y19		4[A]
M19		9	R14		9	W16		4[B]
L20		10	Y16		10	R16		5[A]
M20		11	W14		11	T17		5[B]
M17		12	Y17		12	R17		6[A]
K19		13	Y14		13	R18		6[B]
M18		14	T16		14	V17		7[A]
J19		15	V15		15	W18		7[B]
L16		16	U17		16
K17		17	W15		17
L17		18	U14		18
K18		19	U18		19
H16		20	U15		20
J18		21	U19		21
H17		22	N18		22
H18		23	N20		23
G17		24	N15	PPWA	0
F19		25	L14		1
G18		26	N16		2
F20		27	L15		3
G19		28	M14		4
J20		29	K16		5
G20		30	V18	UART	tx[0]
H20		31	W19		rx[0]
K14		32	N17		tx[1]
H15		33	P15		rx[1]
J14		34	M15	Watchdog	pwm
G15		35	J16	Watchdog	granted

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