Infoportal
Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
| Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
| embedded_systems:zynq7000:mapping_flink2 [2021-09-29 17:33] – Laszlo Arato | embedded_systems:zynq7000:mapping_flink2 [2024-01-05 09:50] (aktuell) – Laszlo Arato | ||
|---|---|---|---|
| Zeile 1: | Zeile 1: | ||
| ====== Pin Mapping for flink2 Configuration ====== | ====== Pin Mapping for flink2 Configuration ====== | ||
| - | {{: | + | {{: |
| <WRAP blindtable 100%> | <WRAP blindtable 100%> | ||
| Zeile 7: | Zeile 7: | ||
| ^FPGA Pin^Flink Device^Flink Channel^ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
| - | |B19|GPIO|0| | + | |M17|GPIO|0| |
| - | |B20|:::|1| | + | |K19|:::|1| |
| - | |A20|:::|2| | + | |M18|:::|2| |
| - | |E17|:::|3| | + | |J19|:::|3| |
| - | |D19|:::|4| | + | |L16|:::|4| |
| - | |D18|:::|5| | + | |K17|:::|5| |
| - | |E19|:::|6| | + | |L17|:::|6| |
| - | |F17|:::|7| | + | |K18|:::|7| |
| - | |L19|:::|8| | + | |H16|:::|8| |
| - | |M19|:::|9| | + | |J18|:::|9| |
| - | |L20|:::|10| | + | |H17|:::|10| |
| - | |M20|:::|11| | + | |H18|:::|11| |
| - | |M17|:::|12| | + | |G17|:::|12| |
| - | |K19|:::|13| | + | |F19|:::|13| |
| - | |M18|:::|14| | + | |G18|:::|14| |
| - | |J19|:::|15| | + | |F20|:::|15| |
| - | |L16|:::|16| | + | |G19|:::|16| |
| - | |K17|:::|17| | + | |J20|:::|17| |
| - | |L17|:::|18| | + | |G20|:::|18| |
| - | |K18|:::|19| | + | |H20|:::|19| |
| - | |H16|:::|20| | + | |K14|:::|20| |
| - | |J18|:::|21| | + | |H15|:::|21| |
| - | |H17|:::|22| | + | |J14|:::|22| |
| - | |H18|:::|23| | + | |G15|:::|23| |
| - | |G17|::: | + | |
| - | |F19|::: | + | ^FPGA Pin^Flink Device^Flink Channel^ |
| - | |G18|:::|26| | + | |N15|PPWA|0| |
| - | |F20|::: | + | |
| - | |G19|::: | + | ^FPGA Pin^Flink Device^Function^ |
| - | |J20|:::|29| | + | |L14|TCRT1000|Trig| |
| - | |G20|:::|30| | + | |N16|:::|Address 0| |
| - | |H20|:::|31| | + | |L15|:::|Address 1| |
| - | |K14|:::|32| | + | |M14|:::|Address 2| |
| - | |H15|:::|33| | + | |K16|:::|Address 3| |
| - | |J14|::: | + | |
| - | |G15|:::|35| | + | |
| </ | </ | ||
| Zeile 72: | Zeile 70: | ||
| |N18|::: | |N18|::: | ||
| |N20|::: | |N20|::: | ||
| - | |||
| - | ^FPGA Pin^Flink Device^Flink Channel^ | ||
| - | |N15|PPWA|0| | ||
| - | |L14|:::|1| | ||
| - | |N16|:::|2| | ||
| - | |L15|:::|3| | ||
| - | |M14|:::|4| | ||
| - | |K16|:::|5| | ||
| ^FPGA Pin^Flink Device^Flink Channel^ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
| Zeile 86: | Zeile 76: | ||
| |N17|::: | |N17|::: | ||
| |P15|::: | |P15|::: | ||
| - | |||
| - | </ | ||
| - | <WRAP blindcell 30%> | ||
| ^FPGA Pin^Flink Device^Function^ | ^FPGA Pin^Flink Device^Function^ | ||
| |M15|Watchdog|PWM| | |M15|Watchdog|PWM| | ||
| |J16|Watchdog|Granted| | |J16|Watchdog|Granted| | ||
| + | |||
| + | </ | ||
| + | <WRAP blindcell 30%> | ||
| ^FPGA Pin^Flink Device^Flink Channel^ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
| Zeile 115: | Zeile 105: | ||
| |T11|ADC128S102|DIN| | |T11|ADC128S102|DIN| | ||
| |T19|::: | |T19|::: | ||
| - | |R19|:::|CS| | + | |R19|:::|CSN| |
| |T12|::: | |T12|::: | ||
| ^FPGA Pin^Flink Device^ADC Pin^ | ^FPGA Pin^Flink Device^ADC Pin^ | ||
| |D20|AD7476|SCLK| | |D20|AD7476|SCLK| | ||
| - | |F16|:::|CS| | + | |F16|:::|CSN| |
| |E18|::: | |E18|::: | ||
| + | |||
| + | ^FPGA Pin^XADC Device^Channel^ | ||
| + | |E17|XADC|0[p]| | ||
| + | |D18|::: | ||
| + | |M19|::: | ||
| + | |M20|::: | ||
| + | |L19|::: | ||
| + | |L20|::: | ||
| + | |B19|::: | ||
| + | |A20|::: | ||
| </ | </ | ||