Infoportal
Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
| Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
| embedded_systems:zynq7000:mapping_flink2 [2021-10-12 11:02] – Urs Graf | embedded_systems:zynq7000:mapping_flink2 [2024-01-05 09:50] (aktuell) – Laszlo Arato | ||
|---|---|---|---|
| Zeile 1: | Zeile 1: | ||
| ====== Pin Mapping for flink2 Configuration ====== | ====== Pin Mapping for flink2 Configuration ====== | ||
| - | {{: | + | {{: |
| <WRAP blindtable 100%> | <WRAP blindtable 100%> | ||
| Zeile 32: | Zeile 32: | ||
| |G15|::: | |G15|::: | ||
| - | ^FPGA Pin^XADC Device^Channel^ | + | ^FPGA Pin^Flink Device^Flink Channel^ |
| - | |E17|XADC|0[p]| | + | |N15|PPWA|0| |
| - | |D18|:::|0[n]| | + | |
| - | |M19|:::|1[p]| | + | ^FPGA Pin^Flink Device^Function^ |
| - | |M20|:::|1[n]| | + | |L14|TCRT1000|Trig| |
| - | |L19|:::|2[p]| | + | |N16|:::|Address 0| |
| - | |L20|::: | + | |L15|:::|Address |
| - | |B19|::: | + | |M14|:::|Address |
| - | |A20|:::|3[n]| | + | |K16|:::|Address |
| </ | </ | ||
| Zeile 70: | Zeile 70: | ||
| |N18|::: | |N18|::: | ||
| |N20|::: | |N20|::: | ||
| - | |||
| - | ^FPGA Pin^Flink Device^Flink Channel^ | ||
| - | |N15|PPWA|0| | ||
| - | |L14|:::|1| | ||
| - | |N16|:::|2| | ||
| - | |L15|:::|3| | ||
| - | |M14|:::|4| | ||
| - | |K16|:::|5| | ||
| ^FPGA Pin^Flink Device^Flink Channel^ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
| Zeile 84: | Zeile 76: | ||
| |N17|::: | |N17|::: | ||
| |P15|::: | |P15|::: | ||
| - | |||
| - | </ | ||
| - | <WRAP blindcell 30%> | ||
| ^FPGA Pin^Flink Device^Function^ | ^FPGA Pin^Flink Device^Function^ | ||
| |M15|Watchdog|PWM| | |M15|Watchdog|PWM| | ||
| |J16|Watchdog|Granted| | |J16|Watchdog|Granted| | ||
| + | |||
| + | </ | ||
| + | <WRAP blindcell 30%> | ||
| ^FPGA Pin^Flink Device^Flink Channel^ | ^FPGA Pin^Flink Device^Flink Channel^ | ||
| Zeile 113: | Zeile 105: | ||
| |T11|ADC128S102|DIN| | |T11|ADC128S102|DIN| | ||
| |T19|::: | |T19|::: | ||
| - | |R19|:::|CS| | + | |R19|:::|CSN| |
| |T12|::: | |T12|::: | ||
| ^FPGA Pin^Flink Device^ADC Pin^ | ^FPGA Pin^Flink Device^ADC Pin^ | ||
| |D20|AD7476|SCLK| | |D20|AD7476|SCLK| | ||
| - | |F16|:::|CS| | + | |F16|:::|CSN| |
| |E18|::: | |E18|::: | ||
| + | |||
| + | ^FPGA Pin^XADC Device^Channel^ | ||
| + | |E17|XADC|0[p]| | ||
| + | |D18|::: | ||
| + | |M19|::: | ||
| + | |M20|::: | ||
| + | |L19|::: | ||
| + | |L20|::: | ||
| + | |B19|::: | ||
| + | |A20|::: | ||
| </ | </ | ||