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| software:flink:flink_example_1 [2015-01-29 22:21] – graf | software:flink:flink_example_1 [Unbekanntes Datum] (aktuell) – gelöscht - Externe Bearbeitung (Unbekanntes Datum) 127.0.0.1 | ||
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| - | ====== flink on Phytec PCM032 Board (mpc5200) ====== | ||
| - | The following example describes in detail how a Phytec PCM032 Board containing a mpc5200 and a FPGA is configured to be used with flink. The FPGA will contain a single channel PWM module and a single channel GPIO modul. | ||
| - | ===== Setup ===== | ||
| - | * Configure the board with a working Linux kernel and root file system or use the system described in [[software: | ||
| - | * Make sure that the device tree blob is up-to-date. It must contain a node for the FPGA sitting on the local plus bus. | ||
| - | * Get necessary sources for the flink project.< | ||
| - | git clone https:// | ||
| - | git clone https:// | ||
| - | |||
| - | ===== Configure the FPGA ===== | ||
| - | Proceed as described in [[software: | ||
| - | * In 5: add a block //gpio// and a block //pwm// to the system. Also add a // | ||
| - | * After 9: the System should now look like: [{{ : | ||
| - | * In 14: choose the pins as follows: | ||
| - | ^signal^dir^pin^ | ||
| - | |clk_clk|in|PIN_H2| | ||
| - | |lpb_ack_n|out|PIN_T11| | ||
| - | |lpb_ad[31]|bidir|PIN_T6| | ||
| - | |lpb_ad[30]|bidir|PIN_N8| | ||
| - | |lpb_ad[29]|bidir|PIN_R9| | ||
| - | |lpb_ad[28]|bidir|PIN_T9| | ||
| - | |lpb_ad[27]|bidir|PIN_R8| | ||
| - | |lpb_ad[26]|bidir|PIN_T8| | ||
| - | |lpb_ad[25]|bidir|PIN_L8| | ||
| - | |lpb_ad[24]|bidir|PIN_L7| | ||
| - | |lpb_ad[23]|bidir|PIN_R7| | ||
| - | |lpb_ad[22]|bidir|PIN_T7| | ||
| - | |lpb_ad[21]|bidir|PIN_R5| | ||
| - | |lpb_ad[20]|bidir|PIN_T5| | ||
| - | |lpb_ad[19]|bidir|PIN_R4| | ||
| - | |lpb_ad[18]|bidir|PIN_T4| | ||
| - | |lpb_ad[17]|bidir|PIN_P4| | ||
| - | |lpb_ad[16]|bidir|PIN_P5| | ||
| - | |lpb_ad[15]|bidir|PIN_R3| | ||
| - | |lpb_ad[14]|bidir|PIN_T3| | ||
| - | |lpb_ad[13]|bidir|PIN_P11| | ||
| - | |lpb_ad[12]|bidir|PIN_N11| | ||
| - | |||
| - | The pins for the PWM output and the GPIO have to be assigned according to your hardware. | ||
| - | |||
| - | lpb_ad[20] Bidir PIN_T5 | ||
| - | lpb_ad[19] Bidir PIN_R4 | ||
| - | lpb_ad[18] Bidir PIN_T4 | ||
| - | lpb_ad[17] Bidir PIN_P4 | ||
| - | lpb_ad[16] Bidir PIN_P5 | ||
| - | lpb_ad[15] Bidir PIN_R3 | ||
| - | lpb_ad[14] Bidir PIN_T3 | ||
| - | lpb_ad[13] Bidir PIN_P11 | ||
| - | lpb_ad[12] | ||
| - | Hint: FPGA side described in [[https:// | ||
| - | |||
| - | TODO: Move to here, add software side | ||