Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung |
software:linux:fpga_loader [2015-06-30 12:58] – abajric | software:linux:fpga_loader [2023-04-11 08:35] (aktuell) – Urs Graf |
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<box 30% right green | QuickLinks> | <box 30% right green | QuickLinks> |
* [[https://github.com/ntb-ch/fpga_loader| Source Code]] | * [[https://gitlab.ost.ch/tech/inf/public/fpga-loader| Source Code]] |
* [[https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cfg/cfg_cf51001.pdf| Configuring Altera FPGAs]] | * [[https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cfg/cfg_cf51001.pdf| Configuring Altera FPGAs]] |
</box> | </box> |
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Altera FPGAs können über 5 Leitungen von einem Microkontroller konfiguriert werden (Passive Serial). Für Linux gibt es ein Kernel Modul, welches über das GPIO Subsystem die Ansteuerung der Signale realisiert. | Altera FPGAs can be configured by a microcontroller using 5 wires (Passive Serial). The FPGA loader is a Linux kernel module which uses the gpio subsystem to drive the signals on the 5 wires. The version on github supports the Colibri module from Toradex (iMX6). For other plattforms you have to change the pin numbers in the source code. |
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| In order to be able to load the FPGA design you have to enable the creation of the RBF file in Quartus under //Device and Pin Options//: |
Um das FPGA Design laden zu können, muss in Quartus zuerst das Erzeugen des RBF-Files in den //Device and Pin Options// aktiviert werden: | |
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{{.:quartus-rbf.png?400|}} | {{.:quartus-rbf.png?400|}} |
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Das RBF-File kann mit dem ''dd'' Befehl auf das FPGA geladen werden: | Make sure to load the kernel modul //fpga_loader.ko// before using. After sucessfully loading the FPGA you have to unload the kernel module in order to use the gpio's as usual. |
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| The RBF file can be loaded with ''dd'': |
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<code> | <code> |
# dd if=design.rbf of=/dev/fpga_loader bs=5M | # dd if=design.rbf of=/dev/fpga_loader bs=5M |
</code> | </code> |
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| ===== Details ===== |
| [[https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-51008.pdf]] shows how the FPGA is configured properly. |
| The timing is as follows {{ :software:linux:timing.pdf |}}. Please note that //Two DCLK falling edges are required after CONF_DONE goes high to begin the |
| initialization of the device.// |
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